Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 165-169

  Mathur, Anmol ^a   Liu, C L ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FAULT TOLERANT COMPUTER SYSTEMS; GRAPH THEORY; LOGIC PROGRAMMING; PROBABILITY;

CONFIGURABLE LOGIC BLOCKS (CLB); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PLACEMENT RECONFIGURATION; SLACK NEIGHBORHOOD GRAPH; TIMING DEGRADATION; YIELD ENHANCEMENT;

LOGIC GATES;

EID: 0029772775     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)