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Volumn , Issue , 1996, Pages 509-514
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Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality
a
a
SIEMENS AG
(Germany)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER SIMULATION;
CONCURRENT ENGINEERING;
INTEGRATION;
RANDOM ACCESS STORAGE;
RANDOM PROCESSES;
REAL TIME SYSTEMS;
SYNCHRONIZATION;
THREE DIMENSIONAL;
BEHAVIORAL MODELING;
DATAPATH;
STEPWISE REFINEMENT;
SYNCHRONOUS CONTROLLERS;
TIME ABSTRACTION;
VERILOG HARDWARE DESCRIPTION LANGUAGES;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
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EID: 0029771868
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (1)
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References (17)
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