Hardware module selection for real time pipeline architectures using probabilistic cost estimation

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1996, Pages 147-150

  Sentieys, O ^a   Diguet, J Ph ^a   Philippe, J L ^a   Martin, E ^a  

^a UNIVERSITÉ DE RENNES 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; PIPELINE PROCESSING SYSTEMS; PROBABILITY; REAL TIME SYSTEMS;

CADDY SYNTHESIS; DATA FLOW GRAPH; PIPELINE ARCHITECTURES; PROBABILISTIC COST ESTIMATION; SEHWA TOOL;

COMPUTER HARDWARE;

EID: 0029771395     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)