Chip and package co-design technique for clock networks

Proceedings of the IEEE Multi-Chip Module Conference

Volumn , Issue , 1996, Pages 160-163

  Zhu, Qing ^a   Dai, Wayne W M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC DELAY LINES; ELECTRIC RESISTANCE; ELECTRIC WIRING; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT LAYOUT; MULTICHIP MODULES; PERMITTIVITY;

CLOCK DISTRIBUTION; CLOCK SKEW; DIELECTRIC PERMEABILITY; FLIP CHIP TECHNOLOGY; SINGLE CHIP MODULES; TIME OF FLIGHT DELAY;

TIMING CIRCUITS;

EID: 0029760780     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)