Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

IEE Proceedings: Computers and Digital Techniques

Volumn 143, Issue 1, 1996, Pages 23-29

  Fujioka, Y ^a   Kameyama, M ^b   Tomabechi, N ^a  

^a HACHINOHE INSTITUTE OF TECHNOLOGY   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

Multi operand multiply additions; Parallel VLSI processor; Reconfiguration; Robot electronics systems; Small delay time

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; FEEDBACK CONTROL; MANIPULATORS; PARALLEL PROCESSING SYSTEMS; SENSORS; SWITCHING CIRCUITS; VLSI CIRCUITS;

DYNAMIC CONTROL; MULTIOPERATED MULTIPLY ADDITION; ROBOT ELECTRONICS SYSTEMS; SMALL DELAY TIME; VERY LONG INSTRUCTION WORD CONTROL METHOD;

INTELLIGENT ROBOTS;

EID: 0029759816     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960103     Document Type: Article

References (11)

1. KAMEYAMA, M., MATSUMOTO, T., EGAMI, H., and HIGUCHI, T.: 'A special-purpose LSI for inverse kinematics computation", Inst. Electron. Inf. Commun. Eng. Japan, 1991, E74, (11), pp. 3829-3837
2. KIM, B., KAMEYAMA, M., and HIGUCHI, T.: 'Parallel VLSI processors for robotics using multiple bus interconnection networks', Inst. Electron. Inf. Commun. Eng. Japan, 1992, E75-A, (6), pp. 712-719
3. CHEN, J.B., FEARING, R.S., ARMSTRONG, B.S., and BURDICK, J.W.: 'NYMPH: a multiprocessor for manipulation applications'. Proceedings of IEEE international conference on Robotics and Automation, 1986, Vol. 3, pp. 1731-1736
4. NIGAM, R., and LEE, C.S.G.: 'A multiprocesor-based controller for the control of mechanical manipulators', IEEE Trans., 1985, RA-1, (4), pp. 173-182
5. CHEN, C.L., LEE, C.S.G., and HOU, E.S.H.: 'Efficient scheduling algorithms for robot inverse dynamics computation on a multiprocessor system', IEEE Trans. Syst. Man Cybern., 1988, 18, (5), pp. 729-743
6. FUJIOKA, Y., KAMEYAMA, M., and HIGUCHI, T.: 'Coordinate transformation VLSI processor for redundant manipulator control', Inst. Electron. Inf. Commun. Eng. Japan, 1992, J75 D-I, (10), pp. 909-916 (in Japanese)
7. FUJIOKA, Y., KAMEYAMA, M., and HIGUCHI, T.: '240MOPS reconfigurable parallel VLSI processor for robot control',Proceedings of IECON'92, IEEE, 1992, Vol. 3, pp. 1385-1390
8. SADAYAPPAN, P., LING, Y.L.C., OLSON, K.W., and ORIN, D.E.: 'A restructurable VLSI robotics vector processor architecture for real-time control', IEEE Trans. Robot. Autom., 1989, 5, (5), pp. 583-599
9. LIN, C.T., and LEE, C.S.G.: 'Fault-tolerant reconfigurable architecture for robot kinematics and dynamics computations', IEEE Trans. Syst. Man Cybern., 1991, 21, (5), pp. 983-999
10. OKUYAMA, H., NAKANO, T., NISHIDA, S., ANDO, E., SATOH, H., and ARITA, S.: 'A 7.5-ns 32K × 8 CMOS SRAM', IEEE J. Solid-State Circuits, 1988, 23, (5), pp. 1054-1059
11. YANG, T.S., HOROWITZ, M.A., and WOOLEY, B.A.: 'A 4-ns 4K × 1-bit two-port BiCMOS SRAM', IEEE J. Solid-State Circuits, 1988, 23, (5), pp. 1030-1040