Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 584-588

  Rullan, M ^a   Ferrer, C ^a   Oliver, J ^a   Mateo, D ^a   Rubio, A ^a  

^a Campus Universitari ^*  (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

CELL LIBRARY DESIGN; IDDQ TESTING STRATEGY; ISSQ TESTING STRATEGY;

CMOS INTEGRATED CIRCUITS;

EID: 0029755804     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)