Application of electron beam lithography for downscaling of SOI-Bipolar and BiCMOS

Microelectronic Engineering

Volumn 30, Issue 1-4, 1996, Pages 31-34

  Sauter, M ^a,b   Bertagnolli, E ^a   Knapek, E ^a   Stemmer, A ^a   Froschle B ^b   Eisele, I ^c   Klose, H ^a  

^a SIEMENS AG   (Germany)

^b Fraunhofer Institut fur Festkorpertechnologie   (Germany)

^c BUNDESWEHR UNIVERSITY MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; ELECTRIC VARIABLES MEASUREMENT; MASKS; METALLIZING; POLYMETHYL METHACRYLATES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; SURFACES;

DOWNSCALING; GUMMEL PLOTS; LITHOGRAPHIC BASE DEFINITION;

ELECTRON BEAM LITHOGRAPHY;

EID: 0029755564     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9317(95)00188-3     Document Type: Article

References (5)

1. S. Verdonckt-Vandebroek et al., IEEE Trans.El.Dev. Vol 38, No.11, pp. 2487-2495, Nov.1991
2. A. Tamba et al., Tech.Dig. IEDM 90, pp. 395-398
3. B. Edholm et al., IEEE Trans.EI.Devices Vol. 40, No.12, pp. 2359-2360 December 1993
4. S. Parke et al, IEDM Tech.Dig 92, pp 453-455
5. J. Lohstroh et al., Solid-State-Electronics, Vol.24 No.9, pp.805-814, 1981