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Volumn 17, Issue 1, 1996, Pages 25-27

The dual gate emitter switched thyristor (DG-EST)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC VARIABLES MEASUREMENT; GATES (TRANSISTOR); MOS DEVICES; SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0029752897     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.475566     Document Type: Article
Times cited : (18)

References (10)
  • 6
    • 0028538818 scopus 로고
    • 550 V,N-channel emitter switched thyristors with an atomic lattice laypot geometry
    • Nov.
    • A. Bhalla and T. P. Chow, "550 V,N-channel emitter switched thyristors with an atomic lattice laypot geometry," IEEE Electron Device Lett., vol. 15, no. 11, pp. 452-454, Nov. 1994.
    • (1994) IEEE Electron Device Lett. , vol.15 , Issue.11 , pp. 452-454
    • Bhalla, A.1    Chow, T.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.