New architecture for high throughput-rate real-time 2-D DCT and the VLSI design

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1996, Pages 219-221

  Chiang, Jen Shiun ^a   Huang, Hsiang Chou ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; IMAGE COMPRESSION; LOGIC DEVICES; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORMS; PROGRAMMABLE LOGIC ARRAY; VIDEO SIGNAL COMPRESSION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029751706     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)