New HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs

European Design Automation Conference - Proceedings

Volumn , Issue , 1996, Pages 126-131

  Binh, Nguyen Ngoc ^a   Imai, Masaharu ^a   Shiomi, Akichika ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; LOGIC GATES; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PROBLEM SOLVING; RANDOM ACCESS STORAGE; ROM;

APPLICATION SPECIFIC INTEGRATED PROCESSORS; BRANCH AND BOUND ALGORITHM; HARDWARE SOFTWARE PARTITIONING ALGORITHM; PIPELINED CPU ARCHITECTURE;

ALGORITHMS;

EID: 0029749454     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)