-
2
-
-
0026220148
-
The synchronous approach to reactive and real-time systems
-
September
-
G. Berry, P. Couronné, and G. Gonthier. The synchronous approach to reactive and real-time systems. IEEE Proceedings, 79, September 1991.
-
(1991)
IEEE Proceedings
, vol.79
-
-
Berry, G.1
Couronné, P.2
Gonthier, G.3
-
4
-
-
0003346051
-
Ptolemy: A framework for simulating and prototyping heterogeneous systems
-
Simulation Software Development, January
-
J. Buck, S. Ha, E.A. Lee, and D.G. Masserschmitt. Ptolemy: a framework for simulating and prototyping heterogeneous systems. Interntional Journal of Computer Simulation, special issue on Simulation Software Development, January 1990.
-
(1990)
Interntional Journal of Computer Simulation
, Issue.SPEC. ISSUE
-
-
Buck, J.1
Ha, S.2
Lee, E.A.3
Masserschmitt, D.G.4
-
5
-
-
0037622735
-
-
Technical Report UCB/ERL M93/48, U.C. Berkeley, June
-
M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli. A formal specification model for hardware/software codesign. Technical Report UCB/ERL M93/48, U.C. Berkeley, June 1993.
-
(1993)
A Formal Specification Model for Hardware/software Codesign
-
-
Chiodo, M.1
Giusto, P.2
Hsieh, H.3
Jurecska, A.4
Lavagno, L.5
Sangiovanni-Vincentelli, A.6
-
8
-
-
33749442564
-
-
CISI Ingenierie, Agence Provence Est, Les Cardoulines B1 06560, Valbonne, France. Esterel V-3, Debug Format Manual, 1988.
-
(1988)
Esterel V-3, Debug Format Manual
-
-
-
14
-
-
84974687699
-
Scheduling algorithms for multiprogramming in a hard-real-time environment
-
January
-
C.I. Liu and J.W. Layland. Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the Association for Computing Machinery, 20(1):46-61, January 1973.
-
(1973)
Journal of the Association for Computing Machinery
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.I.1
Layland, J.W.2
-
16
-
-
0026156694
-
Experiments with a program timing tool based on source-level timing schema
-
C. Y. Park and A. C. Shaw. Experiments with a program timing tool based on source-level timing schema. IEEE Computer, 24(5):48-57, 1991.
-
(1991)
IEEE Computer
, vol.24
, Issue.5
, pp. 48-57
-
-
Park, C.Y.1
Shaw, A.C.2
-
17
-
-
0003934798
-
-
Technical Report UCB/ERL M92/4I, U.C. Berkeley, May
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/4I, U.C. Berkeley, May 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni-Vincentelli, A.10
-
18
-
-
33749448195
-
Formal design verification of digital systems
-
T. Shiple, A. Aziz, F. Balarin, S. Cheng, R. Hojati, T. Kam, S. Krishnan, V. Singhal, H. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Formal design verification of digital systems. In Proceedings of TECHCON, 1993.
-
(1993)
Proceedings of TECHCON
-
-
Shiple, T.1
Aziz, A.2
Balarin, F.3
Cheng, S.4
Hojati, R.5
Kam, T.6
Krishnan, S.7
Singhal, V.8
Wang, H.9
Brayton, R.10
Sangiovanni-Vincentelli, A.11
-
20
-
-
33749442051
-
Problems associated with hardware implementation of software algorithms using behavioral model synthesis
-
September
-
C. E. Stroud. Problems associated with hardware implementation of software algorithms using behavioral model synthesis. In Proceedings of the International Workshop on Hardware-Software Codesign, September 1992.
-
(1992)
Proceedings of the International Workshop on Hardware-Software Codesign
-
-
Stroud, C.E.1
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