Binomial filters

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 12, Issue 1, 1996, Pages 35-50

  Aubury, Matthew ^a   Wayne, L U K ^b  

^a UNIVERSITY OF OXFORD   (United Kingdom)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; IMAGE PROCESSING; LOGIC GATES; NUMERICAL ANALYSIS;

BINOMIAL FILTERS; MULTIDIMENSIONAL FILTERING;

SIGNAL FILTERING AND PREDICTION;

EID: 0029735678     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00936945     Document Type: Article

References (20)

1. S.Y. Rung, VLSI Array Processors, Prentice Hall, 1988.
2. W. Luk, "Systematic pipelining of processor arrays, " G.M. Megson (ed.), Transformational Approaches to Systolic Design, Chapman and Hall Parallel and Distributed Computing Series, 1994, pp. 77-98.
3. W. Luk, "Systematic serialisation of array-based architectures, " Integration, Vol. 14, No. 3, pp. 333-360, 1993.
4. H.K. Nishihara, Real-Time Implementation of a SignCorrelation Algorithm for Image-Matching, Technical Report No. TR-90-02, Teleos Research, 1990.
5. W.M. Wells, "Efficient synthesis of Gaussian filters by cascaded uniform filters, " IEEE Trans. PAMJ, Vol. 8, pp. 234-239, 1992.
6. J. Canny, Finding Edges and Lines in Images, M.Sc. Thesis, Massachusetts Institute of Technology, 1983.
7. D. David, T. Court, J.L. Jacquot, and A. Pirson, "INP 20: An image neighborhood processor for large kernels, " Proc. IAPR Workshop on Computer Vision: Special Hardware and Industrial Applications, University of Tokyo, pp. 241-244, 1988.
8. A. Chehikian and J.L. Crowley, "Fast computation of optimal semi-octave pyramids, " 7th S.C.I.A., Aalborg, August 1991.
9. R.N. Bracewell, The Fourier Transform and its Applications, McGraw-Hill, 1986.
10. S. Guo, W. Luk, and P. Probert, "Developing parallel architectures for range and image sensors, " Proc. IEEE International Conference on Robotics and Automation, pp. 2205-2210, 1994.
11. Xilinx Inc., The Programmable Logic Data Book, 1994.
12. S. Guo and W. Luk, "Compiling Ruby into FPGAs, " W. Luk and W.R. Moore (eds.), Field-Programmable Logic and Applications, Lecture Notes in Computer Science 975, Springer Verlag, pp. 188-197, 1995.
13. G. Jones and M. Sheeran, "Circuit design in Ruby, " J. Staunstrup (ed.), Formal Methods for VLSI Design, North-Holland, pp. 1370, 1990.
14. W. Luk and I. Page, "Parameterising designs for FPGAs, " W.R. Moore and W. Luk (eds.), FPGAs, Abingdon EE & CS Books, pp. 284-295, 1991.
15. A. Lawrence, A. Kay, W. Luk, T. Nomura, and I. Page, "Using reconfigurable hardware to speed up product development and performance, " W. Luk and W.R. Moore (eds.), Field-Programmable Logic and Applications, Lecture Notes in Computer Science 975, Springer Verlag, pp. 111-118, 1995.
16. AlgotronixLtd, CHS2x4 Custom Computer User Manual, 1992.
17. W. Luk, T. Wu, and I. Page, "Hardware-software codeslgn of multidimensional algorithms, " D.A. Buell and K.L. Pocek (eds.), Proc. IEEE Workshop on FPGAs for Custom Computing Machines, JJEEE Computer Society Press, pp. 82-90, 1994.
18. W. Luk and T. Wu, "Towards a declarative framework for hardware-software codesign, " Proc. Third International Workshop on Hardware/Software Codesign, IEEE Computer Society Press, pp. 181-188, 1994.
19. M.C. Mozer, Neural Network Architectures for Temporal Sequence Processing, Predicting the Future and Understanding the Past, Addison Wesley, 1993.
20. H.K. Nishihara, System for Expedited Computation ofLaplacian and Gaussian Filters and Correlation of Their Outputs for Image Processing, United States Patent 5119444, June 1992.