A three-level advanced static VAr compensator

IEEE Transactions on Power Delivery

Volumn 11, Issue 1, 1996, Pages 540-545

  Ekanayake, J B ^a   Jenkins, N ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC TRANSFORMERS; HARMONIC GENERATION; MATHEMATICAL MODELS; MODULATION; POWER CONTROL; REACTIVE POWER;

ADVANCED STATIC VAR COMPENSATOR; SELECTIVE HARMONIC ELIMINATION MODULATION; VOLTAGE SOURCE INVERTER TOPOLOGY;

ELECTRIC INVERTERS;

EID: 0029734907     PISSN: 08858977     EISSN: None     Source Type: Journal    
DOI: 10.1109/61.484140     Document Type: Article

References (4)

1. Gyugyi, L., Hingorani, N.G., Nannery, P.R., Tai, T., "Advanced Static VAr compensator using Gate Turn-off thyristors for Utility Applications." Cigre, Paris, 1990, Paper 23-203.
2. Edwards, C.W., Nannary, P.R., "Advanced Static VAr Compensator Employing GTO Thyristors." IEEE Transactions on Power delivery, Vol 3, No 4, Oct 1988, pp 16221627.
3. Choi, N.S., Cho, J.G., Cho, G.H., "A General Circuit Topology of Multilevel Inverter." IEEE 22nd Annual Power Electronic Specialist Conference, USA, 1991, pp 96-103.
4. Bhagwat, P.M., Stefanovic, V.R., "Generalized structure of a Multilevel PWM Inverter." IEEE Transaction on Industrial Applications, Vol IA-19, No 6, Nov/Dec 1983, pp 1057-1062.