Counter doping into uniformly and heavily doped channel region of sub 0.1 μm SOI MOSFET's

IEEE Electron Device Letters

Volumn 17, Issue 1, 1996, Pages 1-3

  Suzuki, Kunihiro ^a,b   Satoh, Akira ^b   Sugii, Toshihiro ^b  

^a IEEE

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

BACK GATE TRANSISTORS; CHANNEL REGION; COUNTER DOPING; PARASITIC EDGE;

SEMICONDUCTOR DOPING;

EID: 0029733793     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.475558     Document Type: Article

References (6)

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2. K. F. Lee, R. H. Yan, D. Y. Jeon, G. M. Chin, Y. O. Kim, D. M. Tennant, B. Razavi, H. D. Lin, Y. G. Wey, E. H. Westerwick, M. D. Morris, R. W. Johnson, T. M. Liu, M. Tarsia, M. Cerullo, R. G. Swartz, and A. Ourmazd, "Room temperature 0.1 μm CMOS technology with 108 ps gate delay," '93 IEDM, pp. 131-134.
3. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967, p. 297.
4. S. M. Sze, VLSI Technology, 2d ed. New York: McGraw-Hill, 1984, p. 288.
5. W. W. Lin, "A Simple method for extracting average doping concentration in the polysilicon and surface layer near the oxide in polysilicongate MOS structures," IEEE Electron Decvie Lett., vol. 15, pp. 51-53, 1994.
6. S. M. Sze, VLSI Technology, 2d ed. New York: McGraw-Hill, 1984, p. 137.