Characterisation of sub-100 nm-MOS-transistors processed by optical lithography and a sidewall-etchback technique

Microelectronic Engineering

Volumn 30, Issue 1-4, 1996, Pages 431-434

  Horstmann, J T ^a   Hilleringmann, U ^a   Goser, K ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; COMPUTER SIMULATION; ELECTRODES; GATES (TRANSISTOR); GEOMETRICAL OPTICS; MASKS; OPTIMIZATION; PHOTOLITHOGRAPHY; REACTIVE ION ETCHING; SEMICONDUCTING FILMS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS;

GATE ELECTRODES; OPTICAL LITHOGRAPHY; POLYSILICON FILMS; SIDEWALL ETCHBACK TECHNIQUE;

MOSFET DEVICES;

EID: 0029733001     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9317(95)00280-4     Document Type: Article

References (5)

1. D. C. Flanders, N. N. Efremow: "Generation of <50 nm period gratings using edge defined techniques"; J. Vac. Sci. Technol. B 1 (4), Oct. - Dec. 1983; pp. 1105-1108
2. David S. Y. Hsu, N. H. Turner, K. W. Pierson, V. A. Shamamian: "20 nm linewidth platinum pattern fabrication using conformal effusive-source molecular precusor deposition and sidewall lithography"; J. Vac. Sci. Technol. B 10 (5), Sept./Oct. 1992; pp. 2251-2258
3. S. J. Pearton, F. Ren, C. R. Abernathy, J. R. Lothian: "Fabrication of GaN nanostructures by a sidewall-etchback process"; Semicond. Sci. Technol. 9 (1994); pp. 338-340
4. T. Ohzone, M. Yamamoto, H. Iwata, S. Odanaka: "Electrical Characteristics of Scaled CMOSFET's with Source/Drain Regions Fabricated by 7° and 0° Tilt-Angle Implantations"; IEEE Transactions on Electron Devices, Vol. 42, No. 1, January 1995, pp. 70-77
5. J. B. Jacobs and D. Antoniadis: "Channel Profile Engineering for MOSFET's with 100 nm Channel Lengths"; IEEE Transactions on Electron Devices, Vol. 42, No. 5, May 1995, pp. 870-875