On the blocking capability of a planar P-N junction under the influence of a high-voltage interconnection-A 3-D simulation

IEEE Transactions on Electron Devices

Volumn 43, Issue 1, 1996, Pages 165-169

  Falck, Elmar ^a,b   Gerlach, Willi ^c   Korec, Jacek ^a,c  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^b SIEMENS AG   (Germany)

^c DAIMLER AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRONS; IMPURITIES; INTEGRATED CIRCUIT LAYOUT; NUMERICAL METHODS; PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; THREE DIMENSIONAL;

HIGH VOLTAGE INTERCONNECTIONS; IMPACT IONIZATION; IONIZATION INTEGRALS; JUNCTION TERMINAL EXTENSION; NET CHARGE CONCENTRATION; POISSON EQUATION; TWO DIMENSIONAL SIMULATION;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0029732225     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.477608     Document Type: Article

References (6)

1. V. A. K. Temple, "Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique," IEEE Tram: Electron Devices, vol. ED-30, pp. 954-957, 1983.
2. E. Falck, W. Gerlach and J. Korec, "Influence of interconnections onto the breakdown voltage of planar high-voltage p-ti junctions," IEEE Trans. Electron Devices, vol. ED-40, pp. 439-447, 1993.
3. E. Falck, "Untersuchung der Sperrfâhigkeit von HalbleiterBauelementen mittels numerischer Simulation," Ph.D, Dissertation, Technische Universität Berlin, Berlin, Germany, 1994.
4. M. S. Adler, V. A. K. Temple and R. C. Rustay, "Theoretical basis for field calculations on multi-dimensional reverse biased semiconductor devices," Solid-Stare Electron., vol. 25, pp. 1179-1186, 1982.
5. A. G. Chynoweth, "lonization rates for electrons and holes in silicon," Phys. Rev., vol. 109, pp. 1537-1540, 1958.
6. H. Schlangenotto, private communication.