Design considerations for a 7kV/3kA GTO with transparent anode and buffer layer

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn 1, Issue , 1996, Pages 29-34

  Eicher, S ^a   Bauer, F ^a   Zeller, H R ^a   Weber, A ^a   Fichtner, W ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER LAYER; CONDUCTION LOSSES; SWITCHING LOSSES; TRANSPARENT ANODE;

ANODES; COMPUTER SIMULATION; ELECTRIC FIELDS; ELECTRIC LOSSES; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; SPECIFICATIONS;

THYRISTORS;

EID: 0029726762     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)