Low-power design technique for ASICs by partially reducing supply voltage

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1996, Pages 301-304

  Usami, Kimiyoshi ^a   Ishikawa, Takashi ^a   Kanazawa, Masahiro ^a   Kotani, Hiroko ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COMBINATORIAL CIRCUITS; EFFICIENCY; LOGIC CIRCUITS; LOGIC GATES; PERFORMANCE; VOLTAGE CONTROL;

CLUSTERED VOLTAGE SCALING; GATE RESIZING; SUB MICRON AGE; VOLTAGE SUPPLY REDUCTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029726316     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)