FAST: an FPGA-based simulation testbed for ATM networks

IEEE International Conference on Communications

Volumn 1, Issue , 1996, Pages 374-378

  Stiliadis, Dimitrios ^a   Varma, Anujan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; CONGESTION CONTROL (COMMUNICATION); LOGIC GATES; PACKET NETWORKS; SWITCHES; SWITCHING SYSTEMS; TELECOMMUNICATION TRAFFIC;

BUFFER MANAGEMENT; HIGH DENSITY FIELD PROGRAMMABLE GATE ARRAYS; TRAFFIC ARRIVAL PROCESS; TRAFFIC SCHEDULING ALGORITHM;

ASYNCHRONOUS TRANSFER MODE;

EID: 0029723936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)