Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1996, Pages 167-172

  Ohzone, Takashi ^a   Miyakawa, Tetsu ^a   Yabu, Toshiki ^a   Odanaka, Shinji ^a  

^a TOYAMA PREFECTURAL UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC PROPERTIES; ELECTRIC VARIABLES MEASUREMENT; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; ION IMPLANTATION; OPTIMIZATION; SEMICONDUCTOR DEVICE MANUFACTURE;

ELECTRICAL MISMATCH CHARACTERISTICS; SIDE BY SIDE LAYOUT; SOURCE DRAIN ASYMMETRY;

MOSFET DEVICES;

EID: 0029723713     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)