Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors

IEEE MTT-S International Microwave Symposium Digest

Volumn 3, Issue , 1996, Pages 1607-1610

  Dettmer, R ^a   Jenkins, T ^a   Barrette, J ^a   Bozada, C ^a   DeSalvo, G ^a   Ebel, J ^a   Gillespie, J ^a   Havasy, C ^a   Ito, C ^a   Nakano, K ^a   Pettiford, C ^a   Quach, T ^a   Sewell, J ^a   Via, D ^a   Anholt, R ^a  

^a AIR FORCE RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HEAT RESISTANCE; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE STRUCTURES;

EMITTER ELEMENT PLACEMENT; THERMALLY SHUNTED HETEROJUNCTION BIPOLAR TRANSISTORS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0029723030     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)