Iterative test-point selection for analog circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 66-71

  van Spaandonk, J ^a   Kevenaar, T A M ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CALCULATIONS; ITERATIVE METHODS; LINEAR ALGEBRA; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MATRIX ALGEBRA; MEASUREMENT ERRORS; OPTIMIZATION; SENSITIVITY ANALYSIS;

ANALOG CIRCUITS; CIRCUIT UNDER TEST; DECOMPOSITION TECHNIQUE; FUNCTIONAL TESTING; TEST POINT SELECTION;

INTEGRATED CIRCUIT TESTING;

EID: 0029721961     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)