Instruction-set matching and GA-based selection for embedded-processor code generation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 73-76

  Shu, J ^a   Wilson, T C ^a   Banerji, D K ^a  

^a UNIVERSITY OF GUELPH   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTER SIMULATION; DATA STRUCTURES; DIGITAL SIGNAL PROCESSING; GENETIC ALGORITHMS; LINEAR PROGRAMMING; PATTERN RECOGNITION;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS; EMBEDDED PROCESSOR CODE GENERATION; FLAG TABLE; INSTRUCTION SET MATCHING; NEAR OPTIMAL PATTERN SELECTION; PATTERN QUEUE;

PROGRAM PROCESSORS;

EID: 0029721867     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)