Provably good moat routing algorithm

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 86-91

  Ganley, J L ^a   Cohoon, J P ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; PRINTED CIRCUIT DESIGN;

NET ROUTING;

VLSI CIRCUITS;

EID: 0029720302     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)