Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1996, Pages 144-147

  Wilton, Steven J E ^a   Rose, Jonathan ^a   Vranesic, Zvonko G ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COMPUTER ARCHITECTURE; DELAY CIRCUITS; ELECTRIC WIRE; ELECTRIC WIRING; INTEGRATED CIRCUIT TESTING;

BENCHMARK CIRCUITS; EMBEDDED MEMORY ARRAYS; FIELD PROGRAMMABLE GATE ARRAY;

LOGIC GATES;

EID: 0029720038     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)