Analysis of direct wafer bond IGBTs with heavily doped N+ buffer layer

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1996, Pages 339-342

  Tu, S Larry ^a   Tam, Gordon ^a   Tam, Pak ^a   Tsoi, Hak Yam ^a   Taomoto, Aileen ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; ELECTRIC LOSSES; GATES (TRANSISTOR); ION IMPLANTATION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SILICON WAFERS;

DIRECT WAFER BONDING; HEAVILY DOPED BUFFER LAYER; INSULATED GATE BIPOLAR TRANSISTORS; LIFETIME CONTROL; ON STATE VOLTAGE DROP;

BIPOLAR TRANSISTORS;

EID: 0029718654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)