Formal verification of embedded systems based on CFSM networks

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 568-571

  Balarin, Felice ^a   Hsieh, Harry ^a   Jurecska, Attila ^a   Marelli, Magneti ^a   Lavagno, Luciano ^a   Sangiovanni Vincentelli, Alberto ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ERROR ANALYSIS; FINITE AUTOMATA; FORMAL LANGUAGES; MATHEMATICAL MODELS; TIMING CIRCUITS;

CODESIGN FINITE STATE MACHINES (CFSMS); EMBEDDED SYSTEMS; SYNTACTIC MODIFICATION;

COMPUTER NETWORKS;

EID: 0029716981     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240626     Document Type: Conference Paper

References (5)