Clock- and data-recovery IC with demultiplexer for a 2.5Gb/s ATM physical layer controller

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 125-128

  Hansen, Flemming ^a   Salama, C Andre T ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BIPOLAR TRANSISTORS; CLOCKS; CMOS INTEGRATED CIRCUITS; CONTROL EQUIPMENT; DETECTOR CIRCUITS; EMITTER COUPLED LOGIC CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY; DEMULTIPLEXER; PHASE AND FREQUENCY DETECTOR; PHYSICAL LAYER CONTROLLER; TRUE SINGLE PHASED CLOCK;

INTEGRATED CIRCUITS;

EID: 0029716121     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)