Hierarchical strategy of model partitioning for VLSI-design using an improve mixture of experts approach

Parallel and Distributed Simulation, Workshop Proceedings

Volumn , Issue , 1996, Pages 106-113

  Hering, K ^a   Haupt, R ^a   Villmann, Th ^a  

^a UNIVERSITY OF LEIPZIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE; GENETIC ALGORITHMS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; SET THEORY; VLSI CIRCUITS;

CLOCK CYCLE ALGORITHM; COMMUNICATION OVERHEAD; HIERARCHICAL PARTITIONING SCHEME; LOGIC SIMULATION; MODEL PARTITIONING; PARALLEL FUNCTIONAL SIMULATION; REGISTER TRANSFER LEVEL;

COMPUTER SIMULATION;

EID: 0029714219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)