Zener Zap Anti-Fuse Trim in VLSI Circuits

VLSI Design

Volumn 5, Issue 1, 1996, Pages 89-100

  Comer, Donald T ^a  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

Author keywords

anti fuse; mixed signal circuits; precision integrated circuits; trim; VLSI circuits; Zener zap

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; QUALITY CONTROL;

ANTI FUSE TRIM; MIXED SIGNAL CIRCUITS; PRECISION INTEGRATED CIRCUITS; ZENER ZAP;

VLSI CIRCUITS;

EID: 0029713448     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1996/23706     Document Type: Article

References (18)

1. M. I. Cohen, B. A. Unger, and J. F. Milkosky, “Laser Machining of Thin Films and Integrated Circuits,” Bell Syst. Tech. J. 47, 385–405 (1968).
2. S. Harris and D. Wagner, “Laser Trimming on the Chip,” Electronic Packaging and Production, pp. 50–56, February, 1975.
3. G. Erdi, “A Precision Trim Technique for Monolithic Analog Circuits,” IEEE Journal of Solid State Circuits, Vol. SC-10 No. 6, pp. 412–416, December 1975.
4. D. T. Comer, “A Monolithic 12-bit DAC,” IEEE Transactions Circuits and Systems, CAS-25, 504–509, July 1978.
5. D.T. Comer, et. al.: “Selectable Trimming Circuit for Use with a Digital to Analog Converter,” U.S. Patent No. 4, 138, 681, Feb. 6, 1979.
6. D.T. Comer, “Trimming Control Circuit for a Digital to Analog Converter,” U.S. Patent 4, 131, 884, February 14, 1977.
7. R.C. Dobkin, “Integrated Circuit on Chip Trimming,” U.S. Patent No. 4, 225, 878, September 30, 1980.
8. Paul R. Gray, and Robert G. Meyer, “Analysis and Design of Integrated Circuits,” John Wiley and Sons, 1984, p. 389.
9. Alan Grebene, “Bipolar and MOS Analog Integrated circuit Design,” John Wiley and Sons, 1984, Chapter 3.
10. G. Erdi, “Integrated Circuit Having Permanent Adjustment Circuitry which Requires Low Adjustment Current,” U.S. Patent No. 4, 775, 884, October 4, 1988.
11. D. T. Comer, “Apparatus for Multiple Link Trimming in Precision Integrated Circuits,” U.S. Patent No. 4, 777, 471, Oct. 11, 1988.
12. D. T. Comer, “Fusible Link Trim of Precision Integrated Circuits,” Research Report No. SET-VLSI-102.1, May 22, 1992. Penn State Harrisburg Middletown, PA.
13. D. T. Comer, “Introduction to Mixed-Signal VLSI,” Array Publishing, New York, ISBN 0-9638044-0-1, 1994.
14. D.K.Y. Liu, K.L. Chen, H. Tigelaar, J. Paterson, S.O. Chen, “Scaled Dielectric Antifuse Structure for Field-Programmable Gate Array Applications,” IEEE Electron Device Letters, Vol. 12, No. 4, pp. 151–153, April 1991.
15. E. Hamdy, J. McCollum, S. Chen, S. Chiang, S. Eltoukhy, J. Chang, T. Speers, A. Mohsen, “Dielectric Based Antifuse for Logic and Memory ICs,” IEDM Tech. Dig., pp. 786–789, 1988.
16. Jonathon Greene, “Antifuse Field Programmable Gate Arrays,” Proceeding of the IEEE, Vol. 81, No. 7, July 1993, pp. 1042–1056.
17. QUICKLOGIC Corporation, “1994 Data Book,” 2933 Bunker Hill Lane, Santa Clara, CA.
18. R. J. Wong and K.E. Gordon, “Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse,” IEDM Tech. Dig., December, 1993.