VLSI implementation of a neural network classifier

Canadian Conference on Electrical and Computer Engineering

Volumn 1, Issue , 1996, Pages 178-181

  Mandisodza, Robson L K ^a   Luke, David M ^a   Pochec, Przemyslaw ^a  

^a UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; INTERCONNECTION NETWORKS; LEARNING ALGORITHMS; LOGIC CIRCUITS; LOGIC GATES; PATTERN RECOGNITION SYSTEMS; VLSI CIRCUITS;

CONFIGURABLE LOGIC BLOCKS; CONTROL LOGIC BLOCKS; FIELD PROGRAMMABLE GATE ARRAYS; HOPFIELD NETWORK; LOGIC FUNCTIONS; NEURAL NETWORK CLASSIFIER; VERILOG HDL;

NEURAL NETWORKS;

EID: 0029712906     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)