Innovative verification strategy reduces design cycle time for high-end SPARC processor

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 311-314

  Popescu, Val ^a   McNarama, Bill ^a  

^a Metaflow Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT;

DESIGN VERIFICATION; SPARC PROCESSOR; SUPERSCALAR PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0029710519     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240577     Document Type: Conference Paper

References (0)