Maximum power estimation for CMOS circuits under arbitrary delay model

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 763-766

  Wang, Chuan Yu ^a   Chou, Tan Li ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL MATHEMATICS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ENERGY DISSIPATION; ESTIMATION; LOGIC GATES; MATHEMATICAL MODELS; MONTE CARLO METHODS; OPTIMIZATION; RANDOM PROCESSES; VECTORS;

BRANCH AND BOUND TECHNIQUE; CIRCUIT SIMULATION; EXPONENTIAL COMPLEXITY; GATE LIBRARY; GLITCHING ACTIVITY; MAXIMUM POWER DISSIPATION; PROCESS VARIATIONS; ZERO DELAY MODEL;

CMOS INTEGRATED CIRCUITS;

EID: 0029708323     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)