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Volumn 2, Issue , 1996, Pages 465-468
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FPGA based systolic array architectures for computing the discrete Fourier transform
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CORDIC ARITHMETIC;
DISCRETE FOURIER TRANSFORMS;
FIELD PROGRAMMABLE GATE ARRAYS;
PROCESSING ELEMENTS;
SYSTOLIC ARRAY ARCHITECTURE;
TRANSFORM EXECUTION TIMES;
ALGORITHMS;
COMPUTATIONAL METHODS;
COMPUTER SIMULATION;
COMPUTER SYSTEMS;
DIGITAL ARITHMETIC;
DIGITAL FILTERS;
DIGITAL SIGNAL PROCESSING;
FAST FOURIER TRANSFORMS;
LOGIC GATES;
MULTIPLYING CIRCUITS;
RESPONSE TIME (COMPUTER SYSTEMS);
SYSTOLIC ARRAYS;
COMPUTER ARCHITECTURE;
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EID: 0029708261
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (5)
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References (8)
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