Efficient multiple scan chain testing scheme

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 294-297

  Zhang, Z ^a   McLeod, R D ^a  

^a UNIVERSITY OF MANITOBA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; EFFICIENCY; ELECTRIC DELAY LINES; ELECTRIC FAULT LOCATION; FLOWCHARTING; PRINTED CIRCUIT DESIGN; TESTING;

DELAY FAULTS;

VLSI CIRCUITS;

EID: 0029708208     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)