High-speed parallel VLSI-architecture for the (24,12) Golay decoder with optimized permutation decoding

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 61-64

  Cao, Weixun ^a  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DECODING; ERROR CORRECTION; LOGIC DESIGN; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

CARRY SAVE COMPUTATION; CYCLIC SYNDROME CALCULATION; GOLAY DECODER; PERMUTATION; PERMUTATION DECODING; WOLFMANN ALGORITHM;

VLSI CIRCUITS;

EID: 0029707850     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)