Minimum-area floorplanning algorithm for MBC designs

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 56-59

  Mehta, D P ^a   Sherwani, N ^a  

^a UNIVERSITY OF TENNESSEE SPACE INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MIXED BLOCK AND CELLS;

ALGORITHMS; EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; OPTIMIZATION;

PRINTED CIRCUIT DESIGN;

EID: 0029707768     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)