Register allocation technique using guarded PDG

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 1996, Pages 270-277

  Koseki, Akira ^a   Komatsu, Hideaki ^a   Fukazawa, Yoshiaki ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER GRAPHICS; COMPUTER SOFTWARE; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; PROGRAM COMPILERS; SHIFT REGISTERS;

INSTRUCTION LEVEL PARALLEL PROCESSORS; REGISTER ALLOCATION; SCALAR PROCESSORS;

STORAGE ALLOCATION (COMPUTER);

EID: 0029707465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)