5-μm2 full-CMOS cell for high-speed SRAMs utilizing a optical-proximity-effect correction (OPC) technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1996, Pages 146-147

  Ueshima, Masahiro ^a   Mano, Michio ^a   Yoneda, Yutaka ^a   Ichikawa, Tsutomu ^a   Tsudaka, Keisuke ^a   Takahashi, Hiroshi ^a   Yamamura, Ikuhiro ^a   Yabuta, Mitsuo ^a   Motoyoshi, Makoto ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; LOGIC CIRCUITS; LSI CIRCUITS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; TITANIUM NITRIDE; TRANSISTORS;

ANTIREFLECTION LAYER; BORDERLESS CONTACT; OPTICAL PROXIMITY EFFECT CORRECTION TECHNOLOGY; SELF ALIGNED CONTACT; SHEET RESISTANCE; TRENCH ISOLATION;

RANDOM ACCESS STORAGE;

EID: 0029703061     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)