Wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1996, Pages 273-277

  Watanabe, Hajime ^a   Komori, Junko ^a   Higashitani, Keiichi ^a   Mashiko, Yoji ^a   Koyama, Hiroshi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANTENNAS; CMOS INTEGRATED CIRCUITS; HOT CARRIERS; MOSFET DEVICES; NUMERICAL METHODS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING;

ANTENNA TEST STRUCTURES; DRAIN CURRENT; GATE CURRENT; SUBSTRATE CURRENT; WAFER LEVEL MONITORING METHOD;

SEMICONDUCTOR PLASMAS;

EID: 0029701850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)