Floating body effects in partially-depleted SOI CMOS circuits

International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 139-144

  Lu, P F ^a   Ji, J ^a   Chuang, C T ^a   Wagner, L F ^a   Hsieh, C M ^a   Kuang, J B ^a   Hsu, L ^a   Pelella, M M ^a   Chu, S ^a   Anderson, C J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; MOSFET DEVICES; MULTIPLEXING EQUIPMENT; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

CIRCUIT NOISE MARGIN; FLOATING BODY EFFECTS; LOGIC STATE ERROR;

CMOS INTEGRATED CIRCUITS;

EID: 0029701842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)