Scan insertion criteria for low design impact

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 26-31

  Barbagallo, S ^a   Bodoni, M Lobetti ^a   Medina, D ^a   Corno, F ^a   Prinetto, P ^a   Reorda, M Sonza ^a  

^a Italtel ^*  (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; COMPUTER AIDED DESIGN; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SEMICONDUCTING SILICON;

AUTOMATIC TEST PATTERN GENERATION; SCAN INSERTION CRITERIA;

INTEGRATED CIRCUIT TESTING;

EID: 0029700924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)