Pipelining for speed doubling in MDFE

IEEE International Conference on Communications

Volumn 1, Issue , 1996, Pages 561-565

  Kenney, John G ^a   Melas, Michael ^a  

^a OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL FILTERS; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTERSYMBOL INTERFERENCE; LINEAR INTEGRATED CIRCUITS; MAGNETIC DISK STORAGE; STEP RESPONSE;

EQUALIZED DIBIT RESPONSE; FEEDBACK FILTER; MULTI LEVEL DECISION FEEDBACK EQUALIZATION;

EQUALIZERS;

EID: 0029699619     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)