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Volumn , Issue , 1996, Pages 124-131
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Formal verification of delayed consistency protocols
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CACHE MISS RATES;
DATA CONSISTENCY;
DELAYED CONSISTENCY PROTOCOLS;
FORMAL VERIFICATION;
LATENCY TOLERANCE HARDWARE;
MEMORY TRAFFIC;
RELAXED MEMORY CONSISTENCY MODELS;
SHARED MEMORY MULTIPROCESSOR SYSTEM;
SYMBOLIC STATE MODEL;
BUFFER STORAGE;
COMPUTER HARDWARE;
COMPUTER SIMULATION;
FORMAL LANGUAGES;
MATHEMATICAL MODELS;
MULTIPROCESSING SYSTEMS;
NETWORK PROTOCOLS;
PIPELINE PROCESSING SYSTEMS;
SYNCHRONIZATION;
TELECOMMUNICATION TRAFFIC;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
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EID: 0029698252
PISSN: 10636374
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (5)
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References (0)
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