Parallel simulated annealing strategies for VLSI cell placement

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 37-42

  Chandy, John A ^a   Banerjee, Prithviraj ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER AIDED DESIGN; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MARKOV PROCESSES; MULTIPROCESSING SYSTEMS; OBJECT ORIENTED PROGRAMMING; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PERTURBATION TECHNIQUES; SIMULATED ANNEALING;

DISTRIBUTED MEMORY MULTICOMPUTERS; MULTIPLE MARKOV CHAINS; RUNTIME SYSTEMS; SHARED MEMORY MULTIPROCESSOR;

VLSI CIRCUITS;

EID: 0029698154     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)