Parallel hierarchical algorithm for module placement based on sparse linear equations

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 691-694

  Xing, Zhaoyun ^a   Banerjee, Prithviraj ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LINEAR NETWORK SYNTHESIS; MATRIX ALGEBRA; MULTIPROCESSING SYSTEMS; PERTURBATION TECHNIQUES; PROBLEM SOLVING; SIMULATED ANNEALING;

HIERARCHICAL DECOMPOSITION TECHNIQUE; LARGE LAYOUT BENCHMARK CIRCUITS; MODULE PLACEMENT; PARALLEL HIERARCHICAL ALGORITHM; PLACEMENT PROBLEM; PROUD ALGORITHM; SPARSE LINEAR EQUATIONS;

PARALLEL ALGORITHMS;

EID: 0029696499     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)