Quasi delay-insensitive bus for fully asynchronous systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 189-192

  Molina, Pedro A ^a   Cheung, P Y K ^a   Bormann, David S ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SOFTWARE; DELAY CIRCUITS; ELECTRIC WIRING; OBJECT ORIENTED PROGRAMMING; PERFORMANCE; VLSI CIRCUITS;

ASYNCHRONOUS SYSTEMS; INTERCONNECTION DELAY; QUASI DELAY INSENSITIVE BUS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029695933     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)