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Volumn , Issue , 1996, Pages 273-277
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Comparing the performance parameters of two network structures for scalable massively parallel processors
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Author keywords
[No Author keywords available]
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Indexed keywords
ELECTRIC NETWORK TOPOLOGY;
HIERARCHICAL SYSTEMS;
PARALLEL PROCESSING SYSTEMS;
PERFORMANCE;
SCHEDULING;
SYSTEMS ENGINEERING;
TELECOMMUNICATION TRAFFIC;
BIDIRECTIONAL LINEAR ARRAY;
NETWORK DIAMETER;
PACKED EXPONENTIAL CONNECTION NETWORKS;
PERIODICALLY REGULAR CHORDAL RINGS;
ROUTING;
SKIP LINKS;
UNIDIRECTIONAL RING;
COMPUTER NETWORKS;
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EID: 0029694130
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (1)
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References (17)
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