Design verification via simulation and automatic test pattern generation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 174-180

  Al Asaad, Hussain ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ERROR DETECTION; LOGIC CIRCUITS; MATHEMATICAL MODELS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); GATE COUNT ERRORS; GATE SUBSTITUTION ERRORS; INPUT COUNT ERRORS; SINGLE STUCK LINE; WRONG INPUT ERRORS;

LOGIC DESIGN;

EID: 0029547608     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)