ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 543-546

  Ker, Ming Dou ^a   Chang, Hun Hsien ^a   Wu, Chung Yu ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OXIDES; PROTECTION; SEMICONDUCTOR DEVICE STRUCTURES; THYRISTORS;

ELECTROSTATIC DISCHARGE PROTECTION; GATE COUPLE TECHNIQUE; GATE OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 0029547091     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)